An LDMOS transistor conventionally includes an electrically conductive gate enclosed between two electrically insulating spacers, a source region, a drain region, a channel region, and a drift region. A positive potential is applied to the gate, which causes the flow of electrons from the source region to the drain region through the channel region of the LDMOS transistor. Due to the insulating nature of the spacers, they do not act as part of the gate, and the gate voltage can be applied only through the gate and not through the spacers.
A conventional LDMOS transistor 100, as described above, is illustrated in FIG. 1. LDMOS transistor 100 includes an n-type buried layer 104 formed on a p-type substrate 102. An n-type epitaxial layer 106 is grown on n-type buried layer 104, and field oxide layers 108a and 108b are formed on n-type epitaxial layer 106 to define the active region of LDMOS transistor 100. Typically, the active region of LDMOS transistor 100 is the region on n-type epitaxial layer 106 where LDMOS transistor 100 is being fabricated or formed.
LDMOS transistor 100 also includes a p-well 110 in which a source region 112 is formed. P-well 110 can be formed through ion implantation or diffusion of any p-type element such as boron. Similarly, the source region 112 can also be formed through ion implantation or diffusion of any n-type element such as arsenic. Similar arsenic implantation can be used to form a drain region 114 of LDMOS transistor 100.
Further, LDMOS transistor 100 includes a gate 116, for example, a polysilicon gate that is partially over n-type epitaxial layer 106 and partially over p-well 110. As shown in FIG. 1, gate 116 is isolated from n-type epitaxial layer 106 and p-well 110 by a thin dielectric layer 118, which can be, for example, a thin silicon oxide (SiO2) layer. Further, on the sidewalls of gate 116, spacers 120a and 120b are formed. These spacers are non-conductive in nature and can be formed by using dielectric material such as silicon oxide (SiO2) or nitride. Those ordinarily skilled in the art will appreciate that the region under the spacers is lightly doped N-region, commonly known as NLDD (n-type lightly doped diffusion), but is not shown for simplicity.
Typically, whenever a preset positive gate voltage is applied at gate 116, electrons (minority carriers) present in p-well 110 are attracted toward gate 116, and consequently a channel region 122 is formed. Channel region 122 connects source region 112 to drift region 124 of LDMOS transistor 100. When drain-to-source voltage (not shown in FIG. 1) is applied to LDMOS transistor 100, the electrons present in source region 112 travel through channel region 122 and drift region 124 to drain region 114, thus enabling the flow of electrons from the source to the drain in LDMOS transistor 100.
Conventional LDMOS transistor 100, as described above, has the limitation of high parasitic capacitance and channel resistance. The parasitic capacitance of LDMOS transistor 100 is due to the “capacitor” formed between gate 116 and channel region 122. The value of the parasitic capacitance is directly related to the product of the width (not shown in FIG. 1) and the length of channel region 122. Further, the channel resistance of LDMOS transistor 100 is due to the resistance offered by channel region 122, and its value is also related to the length and the width of channel region 122.
The high parasitic capacitance and channel resistance of LDMOS transistor 100 causes the RC constant of LDMOS transistor 100 to increase, and hence the time required for charging and discharging of parasitic gate capacitor of LDMOS transistor 100 also increases. This hampers the performance of LDMOS transistor 100, and the speed of the circuit which utilizes it also decreases. Therefore, continuous efforts are being made to reduce the parasitic capacitance and channel resistance of LDMOS transistor 100.
To overcome the above-mentioned problems, the present invention provides an LDMOS transistor that has much lower channel resistance and parasitic capacitance than that of the prior art LDMOS transistors. A method to fabricate the said LDMOS transistor is also provided.